In the field of digital logic, extensive use is made of well known and highly developed CMOS (complimentary metal-oxide semiconductor) technology. As CMOS has begun to approach maturity as a technology, there is an interest in alternatives that may lead to higher performance in terms of speed, power dissipation computational density, interconnect bandwidth, and the like. An alternative to CMOS technology comprises superconductor based single flux quantum circuitry, utilizing superconducting Josephson junctions, with typical signal power of around 4 nW (nanowatts), at a typical data rate of 20 Gb/s (gigabytes/second), or greater, and operating temperatures of around 4° Kelvin.
Superconductor integrated circuit (IC) layout has typically treated active interconnects similar to the logic gates, with both interconnect and gates containing inductive wires that could be drawn differently in every instance to make connections. This does not map well onto a conventional place-and-route design flow in which gates and active interconnects are quite different with gates being placed first and active interconnects routed between gates. Another IC layout technique assures that gates and active interconnect cells both conform to a standard size, and all connections are made through adjacent cells. However, the overhead in terms of device count, density, and lost performance is very high.